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OKI Semiconductor ML87V2103
GENERAL DESCRIPTION
PEDL87V2103DIGEST-01
Issue Date: Jan. 20, 2003
Preliminary
Video Signal Noise Reduction and Rate Conversion IC with a Built-in 3.9 Mbit Field Memory
The ML87V2103 comprises a 3.9 Mbit field memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise and double the conversion speed. There is an automatic noise reduction mode that detects the noise level in the input video data to set the optimum noise reduction. There are two ways to double the conversion speed: progressive conversion that doubles the number of lines by doubling the horizontal direction frequency and flicker-free conversion that doubles both the vertical and horizontal direction frequencies.
FEATURES
* Built-in memory: 3.9 Mbit filed memory x 1 unit * Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656): 14.75/29.5 MHz * Maximum output operating frequency: 29.5 MHz (double-speed conversion) * Power supply voltage : 3.3 V 0.3 V * Input pin: TTL-5V tolerant (5 V withstand voltage) * Input/output pins: Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage) * Output pin: LVCMOS (3.3 V) * Input data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2) YCbCr (8 bits (YCbCr)) (4:2:2) ITU-R BT.656 (8 bits (YCbCr)) * Output data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2) * Serial bus: I2C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps) * Internal memory controller: Input: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1 Output: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1, 625/50 Hz 1:1, 525/60 Hz 1:1, 625/100 Hz 2:1, 525/120 Hz 2:1 Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768 * Sync generator (for output): Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1, 625/50 Hz 1:1, 525/60 Hz 1:1, 625/100 Hz 2:1, 525/120 Hz 2:1. Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768 * Field-recursive noise reduction: Noise detection and subtraction (with horizontal motion compensation) Automatic noise reduction mode
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OKI Semiconductor
ML87V2103
* Double-speed conversion data interpolation: 2-line linear filter (progressive, flicker-free) Inter-field stationary compensation (progressive *with I/O phase control applied) * Package: 100 pin QFP (QFP100-P-1420-0.65-BK4)
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
BLOCK DIAGRAM
R_Port2 x16
YI0-7 CI0-7
x16
Input Process Block + 3D NR
x16 W_Port 7ports Field Memory (3.9Mbits)
R_Port3 x16 R_Port4 x16 R_Port5 x16 R_Port6 x16
x16 R_Port1
Output Process Block + Line Filter
x16
YO0-7 CO0-7
Control signals IICLK ICLK IVS IHS Memory Controller + NR Controller + Line Filter Controller
IV IF
OCLK OE OVS OHS HREF CLKO
SCL SDA SLA1 SLA2 MODE0-3 SSG TEST1-6 RESET
I2C-bus I/F Register
Control Signals
Output Sync. Generator
INT
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OKI Semiconductor
ML87V2103
PIN CONFIGURATION (TOP VIEW)
RESET
OCLK
N.C.
N.C.
N.C.
N.C.
N.C.
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
52
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
VDD
VDD
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VSS N.C. N.C. OE N.C. N.C. N.C. N.C. TEST5 VDD TEST4 TEST3 TEST2 TEST1 N.C. N.C. TEST6 MTEST SELF
VDD
51
VSS
VSS
VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
50 49 48 47 46 45 44 43 42
VSS HREF OVS OHS INT SSG N.C. TEST7 VDD N.C. VSS VDD CLKO MODE3 MODE2 MODE1 MODE0 IHS IVS VSS
ML87V2103
(QFP100-P-1420-0.65-BK4)
41 40 39 38 37 36 35 34 33 32 31
VSS 100
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9
VDD
VDD
N.C.
N.C.
N.C.
SLA1
SLA2
SDA
ICLK
N.C.
SCL
VDD
YI7
YI6
YI5
YI4
YI3
YI2
YI1
VSS
YI0
VSS
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
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OKI Semiconductor
ML87V2103
PIN DESCRIPTIONS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Symbol VDD N.C. N.C. VSS SDA SCL SLA1 SLA2 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 VDD ICLK VSS CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 N.C. N.C. VDD VSS IVS IHS MODE0 MODE1 MODE2 MODE3 CLKO VDD VSS N.C. I/O -- -- -- -- I/O I I I I I I I I I I I -- I -- I I I I I I I I -- -- -- -- I I I I I I O -- -- -- Pad Remarks IO&CORE Pin Description Power supply 3.3 V Unused pin Unused pin Ground I2C-bus data pin I2C-bus clock pin Slave address setting pin Slave address setting pin Luminance signal input pin bit 7 (MSB) Luminance signal input pin bit 6 Luminance signal input pin bit 5 Luminance signal input pin bit 4 Luminance signal input pin bit 3 Luminance signal input pin bit 2 Luminance signal input pin bit 1 Luminance signal input pin bit 0 (LSB) Power supply 3.3 V Input system clock pin Ground Color difference signal input pin bit 7 (MSB) Color difference signal input pin bit 6 Color difference signal input pin bit 5 Color difference signal input pin bit 4 Color difference signal input pin bit 3 Color difference signal input pin bit 2 Color difference signal input pin bit 1 Color difference signal input pin bit 0 (LSB) Unused pin Unused pin Power supply 3.3 V Ground Input system vertical sync signal input pin Input system horizontal sync signal input pin Mode setting pin - bit 0 Mode setting pin - bit 1 Mode setting pin - bit 2 Mode setting pin - bit 3 Clock output (I2C-bus control possible) Power supply 3.3 V Ground Unused pin
IO&CORE Schmitt(IN)/ OpenDrain(OUT) Schmitt pull-down 50k pull-down 50k
IO&CORE IO&CORE pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k
IO&CORE IO&CORE Schmitt pull-down 50k Schmitt pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k IO&CORE IO&CORE
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OKI Semiconductor
ML87V2103
No. 42 43 44 45 46
Symbol VDD TEST7 N.C. SSG INT
I/O -- I -- I I
Pad Remarks IO&CORE pull-down 50k pull-down 50k pull-down 50k Schmitt(IN) pull-down 50k Schmitt(IN) pull-down 50k IO&CORE IO only
Pin Description Power supply 3.3 V Test input pin Unused pin Internally generated sync signal mode setting pin Output system sync signal input/output select setting pin 0: OVS, OHS input mode 1: OVS, OHS internally generated output mode Output system horizontal sync signal input/output pin Output system vertical sync signal input/output pin Data output horizontal reference signal output pin Ground Power supply 3.3 V Color difference signal output pin - bit 0 (LSB) Color difference signal output pin - bit 1 Color difference signal output pin - bit 2 Color difference signal output pin - bit 3 Ground Color difference signal output pin - bit 4 Color difference signal output pin - bit 5 Color difference signal output pin - bit 6 Color difference signal output pin - bit 7(MSB) Power supply 3.3 V Output system clock pin Ground Luminance signal output pin - bit 0 (LSB) Luminance signal output pin - bit 1 Luminance signal output pin - bit 2 Luminance signal output pin - bit 3 Power supply 3.3 V Luminance signal output pin - bit 4 Luminance signal output pin - bit 5 Luminance signal output pin - bit 6 Luminance signal output pin - bit 7 (MSB) Ground Unused pin Unused pin Unused pin Unused pin Unused pin System reset input pin (0 active) 0: System reset 1: Normal operation Apply ICLK cycle one and more time during "0" level after VDD voltage has reached the specified level in System reset operation.
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
OHS OVS HREF VSS VDD CO0 CO1 CO2 CO3 VSS CO4 CO5 CO6 CO7 VDD OCLK VSS YO0 YO1 YO2 YO3 VDD YO4 YO5 YO6 YO7 VSS N.C. N.C. N.C. N.C. N.C. RESET
I/O I/O O -- -- O O O O -- O O O O -- I -- O O O O -- O O O O -- -- -- -- -- --
IO only
IO only IO only
IO only
IO only
79
I
Schmitt
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
No. 80 81 82 83
Symbol VDD VSS N.C. N.C.
I/O -- -- -- --
Pad Remarks IO&CORE IO&CORE
84
OE
I
pull-down 50k
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
N.C. N.C. N.C. N.C. TEST5 VDD TEST4 TEST3 TEST2 TEST1 N.C. N.C. TEST6 MTEST SELF VSS
-- -- -- -- I -- I I I I -- -- I I I --
pull-down 50k IO&CORE pull-down 50k pull-down 50k pull-down 50k pull-down 50k
pull-down 50k pull-down 50k pull-down 50k IO&CORE
Pin Description Power supply 3.3 V Ground Unused pin Unused pin Output enable input pin 0: data disable 1: data enable *Set to "1" during normal use. Unused pin Unused pin Unused pin Unused pin Test input pin - bit 5 (0: normal operation, 1: test mode) Power supply 3.3 V Test input pin - bit 4 (0: normal operation, 1: test mode) Test input pin - bit 3 (0: normal operation, 1: test mode) Test input pin - bit 2 (0: normal operation, 1: test mode) Test input pin - bit 1 (0: normal operation, 1: test mode) Unused pin Unused pin Test input pin - bit 6 (0: normal operation, 1: test mode) Memory test input pin - bit 2 (0: normal operation, 1: test mode) SELF REFRESH (0: stop, 1: Normal operation) Ground
Notes: Keep the test mode pins set to 0 or leave them open.
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OKI Semiconductor
ML87V2103
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power supply voltage Input pin voltage Output pin short-circuit current Power dissipation Operating temperature Storage temperature Symbol VDD VI IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C -- -- Rating -0.3 to 4.6 -0.3 to 7.0 50 1 0 to 70 -50 to 150 Unit V V mA W C C
Recommended Operating Conditions
Parameter Power supply voltage Power supply voltage Operating temperature Symbol VDD VSS Ta Min. 3.0 0 0 Typ. 3.3 0 -- Max. 3.6 0 70 Unit V V C
Pin Capacitance
(VCC = 3.3 V 0.3 V, f = 1 MHz, Ta = 25C) Parameter Input capacitance Input/output capacitance (OVS, OHS) Input/output capacitance (SDA) Output capacitance Symbol Ci Cio1 Cio2 Co Min. -- -- -- -- Max. 10 10 10 10 Unit pF pF pF pF
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OKI Semiconductor
ML87V2103
DC Characteristics
(Ta = 0 to 70C) Parameter H level input voltage L level input voltage Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS, RESET) Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS, RESET) Hysteresis voltage width H level input current (pull-down) Input leakage current H level output voltage (other than SDA) L level output voltage (other than SDA) L level output voltage (N-Ch.OD) (SDA) Output leakage current Symbol VIH VIL Vt+ Vt- Vh IIH IIL VOH VOL VOOL IOL Condition -- -- -- -- -- 50 k Pull Down TTL IOH = -4 mA IOL = 4 mA IOL = 4 mA 0 Vout VDD Output disabled ICLK: 29.5 MHz OCLK: 29.5 MHz Output disabled Input pin = VIL Min. 2.0 -0.3 -- 0.8 0.1 20 -10 2.4 0 0 -10 Max. 5.5 0.8 2.0 -- -- 200 10 VDD 0.4 0.4 10 Unit V V V V V A A V V V A
Supply current (during operation) Supply current (during standby)
IDD1 IDD2
-- --
120 5
mA mA
AC Characteristics
(Ta = 0 to 70C) Parameter ICLK clock cycle time ICLK clock duty ratio ICLK system input set-up time ICLK system input hold time OCLK clock cycle time OCLK clock duty ratio OCLK system input set-up time OCLK system input hold time OCLK system output delay time CLKO delay time Data through time Symbol tICLK dtICLK tIISU tIIH tOCLK dtOCLK tOISU tOIH tOOD tCKD tDIDO Condition -- -- -- -- -- -- -- -- CL = 30 pF CL = 30 pF CL = 20 pF Min. 33 40 5 3 33 40 5 3 5 4 5 Max. -- 60 -- -- -- 60 -- -- 25 20 20 Unit ns % ns ns ns % ns ns ns ns ns
*1: ( ) indicates the input internal system clock cycle. Note 1: Measurement conditions Output comparison level: VOH = 1.5 V, VOL = 1.5 V Input voltage level: VIH = 3.0 V, VIL = 0.0 V Note 2: .When writing input data to the memory, compensation is applied from the second input system vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and when RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.) Note 3: .When reading output data from the memory, compensation is applied from the second output system vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and when RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.)
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
CIRCUIT APPLICATION EXAMPLE
Application Example 1 Mode setting: Open Slave address: 1011100 Input format: 16-bit YCbCr (Register setting: DISEL = 0, R656 = 0)
3.3V
I2C-bus MATER CONTROLLER
VDD SDA SCL OE 84
VIDEO IN
DIGITAL DECODER (ML86V7666)
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 IVS IHS
1,17,30, 39,51,61, 68,80,90
5 6
9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 32 33
ML87V2103
72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38
YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0 HREF OVS OHS CLKO
SCAN CONVERTER (ML87V2301)
ICLK
GND
OCLK
System Reset
79
CX
62
18
4,19,31, 40,50,56, 63,73,81, 100
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
Application Example 2 Mode setting: Open Slave address: 1011100 Input format: ITU-R BT656 (Register setting: DISEL = 0, R656 = 1)
3.3V
I2C-bus MATER CONTROLLER
SDA SCL VDD OE 84
VIDEO IN
DIGITAL DECODER (ML86V7666)
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 OPEN OPEN ICLK
1,17,30, 39,51,61, 68,80,90
5 6
9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 32 33
ML87V2103
72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38
YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0 HREF OVS OHS CLKO
SCAN CONVERTER (ML87V2301)
79
GND
GND
System Reset
OCLK
CX
62
18
4,19,31, 40,50,56, 63,73,81, 100
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
PACKAGE DIMENSIONS
(Unit: mm)
QFP100-P-1420-0.65-BK4
Mirror finish
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.54 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The QFP is a surface mount type package, which is very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
REVISION HISTORY
Document No.
PEDL87V2103DIGEST-01
Date
Jan.20, 2003
Page Previous Current Edition Edition
- -
Description
Preliminary edition 1
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PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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